1. Field of the Invention
The present invention relates to an image sensor, more specifically, to a complementary metal oxide semiconductor (CMOS) image sensor and manufacturing method thereof.
2. Description of the Related Art
An image sensor, as a kind of semiconductor device, transforms optical images into electrical signals. Image sensors can be generally classified into a charge coupled device (CCD) and a CMOS image sensor.
Conventionally, a CCD comprises a plurality of photo diodes arranged in the form of matrix to transform optical signal into electrical signal, a plurality of vertical charge coupled devices (VCCDs) formed between the photo diodes to transmit charges generating in each photo diode in a vertical direction, a plurality of horizontal charge coupled devices (HCCDs) for transmitting charges transmitted from each VCCDs in a horizontal direction, and a sense amplifier for sensing charges transmitted in the horizontal direction to output electrical signals.
It has been generally known that CCDs have complicated operational mechanisms and high power consumption. In addition, its manufacturing method is relatively complicated, because multiple steps of photolithography processes are required. Especially, it is difficult to integrate a CCD with other devices such as control circuits, signal processing circuits, analog/digital converter, etc., on a single chip. Such disadvantages of CCDs may hinder miniaturization of products containing a CCD.
In order to overcome above described disadvantages of CCDs, CMOS image sensors have been recently developed in the oncoming generation(s) of image sensors. A CMOS image sensor comprises MOS transistors formed in a semiconductor substrate by CMOS fabrication technologies. In CMOS image sensor, the MOS transistors are formed relative to the number of unit pixels, along with peripheral circuits such as control circuits, signal processing circuits, and the like. CMOS image sensor employs a switching mode that MOS transistors successively detect the output of each pixel.
More specifically, a conventional CMOS image sensor may comprise a photo diode and a certain number of MOS transistors in each pixel, thereby successively detecting electrical signals of each pixel in a switching mode to express a given image.
The CMOS image sensor has advantages such as low power consumption and relatively simple fabrication process. In addition, the CMOS image sensor can be integrated with control circuits, signal processing circuits, analog/digital converter(s), etc., because such circuits can be manufacturing using CMOS manufacturing technologies, which enables miniaturization of products. CMOS image sensors have been widely used in a variety of applications such as digital still cameras, digital video cameras, and the like.
Meanwhile, CMOS image sensors can be classified into 3T, 4T, 5T types, etc., according to the number of transistors in a unit pixel. The 3T type CMOS image sensor comprises one photo diode and three transistors, and the 4T type comprises one photo diode and four transistors. Here, a unit pixel layout of the 3T type CMOS image sensor is configured as follows.
FIG. 1 is a circuit diagram of a conventional CMOS image sensor, and FIG. 2 is a layout illustrating a unit pixel in the conventional 3T type CMOS image sensor.
As shown in FIG. 1, a unit pixel of the conventional 3T type CMOS image sensor comprises one photo diode PD and three NMOS transistors T1, T2, and T3. A cathode of the photo diode PD is connected to a drain of the first NMOS transistor T1 and a gate of the second NMOS transistor T2.
Especially, sources of the first and second NMOS transistors T1 and T2 are connected to a supply terminal (VR) for supplying a standard voltage, and a gate of the first NMOS transistor T1 is connected to a reset terminal for supplying a reset signal (RST).
In addition, a source of the third NMOS transistor T3 is connected to a drain of the second NMOS transistor T2, and a drain of the third NMOS transistor T3 is connected to a detecting circuit (not shown) via a signal line. Furthermore, a gate of the third NMOS transistor T3 is connected to a select signal line SLCT.
Here, the first NMOS transistor T1 is a reset transistor Rx for resetting photoelectrons collected in the photo diode PD. The second NMOS transistor T2 is a drive transistor Dx functioning as a source follower buffer amplifier. In addition, the third NMOS transistor T3 is a select transistor Sx functioning as a switch and addresser.
In the conventional 3T type CMOS image sensor, as shown in FIG. 2, one photo diode 20 is formed in a large portion of a defined active region 10, and three gate electrodes 120, 130, and 140 of the first to third transistors are respectively formed to be overlapped in other portion of the active region 10.
The first gate electrode 120 constitutes the reset transistor Rx. The second gate electrode 130 constitutes the drive transistor Dx. The third gate electrode 140 constitutes the select transistor Sx.
Here, dopant ions are implanted in the active region 10 where each transistor is formed, except for the portion of active region below each gate electrodes 120, 130, and 140, to form source and drain regions of each transistor.
Here, a supply voltage Vdd is applied to source/drain regions between the reset transistor Rx and the drive transistor Dx, and the source/drain regions formed at one side of the select transistor Sx is connected to detecting circuits (not shown).
The above-described gate electrodes 120, 130, and 140 are respectively connected to signal lines, and each signal line is connected to external driving circuits via predetermined pads, even which are not shown.
FIGS. 3a to 3e are cross-sectional views successively illustrating a conventional method for manufacturing a CMOS image sensor, in view of III-III′ line in FIG. 2.
As shown in FIG. 3a, a low concentration of P− type epitaxial layer 62 is formed on a heavy concentration of a P++ type semiconductor substrate 61, using an epitaxial process. Here, the low concentration of P− type epitaxial layer 62 is formed in a thickness of 4˜7 μm.
Subsequently, after photolithographically masking an active region and exposing an isolation region on the semiconductor substrate 61, an isolation layer 63 is formed in the isolation region using a shallow trench isolation (STI) process or a local oxidation of silicon (LOCOS) process.
Next, a gate insulating layer 64 and a conductive layer (e.g., a heavy doped polysilicon layer) are deposited on the entire surface of the epitaxial layer 62, in successive order. The conductive layer and the gate insulating layer 64 are selectively patterned using photolithography and etching processes, thus forming the gate electrode 65.
Referring to FIG. 3b, a first photoresist layer 66 is applied over the entire surface of the semiconductor substrate 61 including the gate electrode 65, and then it is patterned using exposure and development processes, thus covering the photo diode region and exposing the transistor region where source/drain regions will be formed.
Using the first photoresist pattern 66 as a mask, a low concentration of N-type dopant ions are implanted in the exposed transistor region to form a low concentration of N-type diffusion region 67.
As shown in FIG. 3c, after removal of the first photoresist pattern 66, a second photoresist layer 68 is applied over the semiconductor substrate 61, and then it is patterned using exposure and development processes, thus exposing the photo diode region.
Then, using the second photoresist pattern 68 as a mask, a low concentration of N-type dopant ions are implanted in the exposed photo diode region of the epitaxial layer 62, thus forming a low concentration of N-type diffusion region 69.
Here, the low concentration of N-type diffusion region 69 is preferably formed at a depth greater than that of the low concentration of N-type diffusion region 67, using a higher implantation energy than that used to form N-type diffusion region 67.
Preferably, the N-type diffusion region 69 is formed deeper to improve the sensitivity of the image sensor.
Here, the N-type diffusion region 69 functions as a source of the reset transistor, referred to as Rx in FIGS. 1 and 2.
In the above-described structure of CMOS image sensor, a reverse bias is applied between the N-type diffusion region 69 of the photo diode and the low concentration of P-type epitaxial layer 62, thus resulting in a depletion layer where electrons are generated by a light. When the reset transistor Rx turns off, the generated electrons lower the potential of the drive transistor Dx. Lowering of potential of the driver transistor proceeds continuously from turn-off of the reset transistor Rx, thus resulting in potential difference. The image sensor can be operated by detecting the potential difference as a signal.
As shown in FIG. 3d, after removing the second photoresist pattern 68, an insulating layer is formed over the entire surface of the substrate 61. Then, an etch-back process is preformed on the insulating layer to form insulating sidewalls 70 on both sides of the gate electrode 65.
A third photoresist layer 71 is then formed over the entire surface of the substrate 61, and then it is patterned by exposure and development processes to cover the photo diode region and expose the transistor source/drain regions.
Using the third photoresist pattern 71 as a mask, a high concentration of N-type dopant ions are implanted in source/drain regions to form a high concentration of N-type diffusion region 72, i.e., a N+ type diffusion region.
As shown in FIG. 3e, after removing the third photoresist pattern 71, a fourth photoresist layer 73 is applied over the entire surface of the substrate 61, and then it is patterned by exposure and development processes to expose the photo diode region.
Subsequently, using the photoresist pattern 73 as an etching mask, P-type dopant ions are implanted in the photo diode region where the N-type diffusion region 69 is formed, thus forming a P0 type diffusion region 74 in the vicinity of the surface of the epitaxial layer 62.
The above-described conventional CMOS image sensor has disadvantages due to increase of dark currents, such as deterioration of device performances (e.g., charge storage capability).
Here, dark currents, as a kind of noise appearing in a displayed image, are induced by current leakage that can be mainly generated in the photo diode region.
In general, the current leakage may appear in interface trap defects in the vicinity of the sidewall of the isolation layer, and in surface defects of the photo diode.
Conventionally, in order to remove the interface trap defects arousing the dark current, the device is annealed in a furnace to join dangling bonds of silicon with hydrogen. However, Si—H bonds are weak to be easily broken during operation of the device.